Heat is becoming a critical bottleneck to the performance and reliability of proposed microelectronic systems. Thermal issues are extremely important to the successful implementation of most modern electronics, especially as we shift to high power density GaN and SiC devices. In most state of the art thermal management approaches for high power density power amplifiers (PA), heat removal from the chip and heat spreading away from the junction is effectively being accomplished from one side of the chip only. Current approaches also rely on thermal interface materials (TIM) (thermal greases, eutectic solders), and heat spreaders for power amplifier attachment to the heat sink resulting in large number of thermal interfaces, potential for thermal voids between the PA and the heat sink and increased assembly costs.
The prior art approaches for cooling GaN devices are summarized in Table 1 below.
TABLE 1Prior ArtSingle side (backside) heatspreading and coolingGaN device junctions (fieldplate or T-gate) areencapsulated in low thermalconductivity materials (air,silicon nitride, etc)GaN PA mounted on heat spreaderand heat sink using eutecticsolders or similar thermalinterface materials whichincrease the system thermalresistance. Potential of voidsin interface layers increaserisk of hot-spot formation.Surface enhancement structures(micro-channels, fins etc)machined on heat sink
Removing heat is critical for the performance and reliability of microelectronic circuits and systems. The situation worsens as the sizes of the microelectronic systems reduce and their power consumption increases due to added functionality. Novel wide-bandgap GaN and SiC devices operate at much higher power densities compared to Si and GaAs devices and also generate more heat. In addition to that the trend for dimensional scaling and 3D integration (size and weight reduction) creates a very challenging environment for all microelectronic systems.
Advances in silicon micromachining, micro-molding, material science (compound heat sinks with matched CTE, thermoplastic TIM etc) and material growth (CVD grown carbon nano-tubes and thin film diamond) over the last decade have significantly increased the efficiency and heat extraction ability of micro-cooling systems. However, none of these technologies are adequate for wide band gap semiconductors (GaN and SiC) which are generating heat fluxes in excess of 1 kW/cm2 and none simultaneously addresses packaging, interconnection and cooling. In addition the prior art does not address a fabrication process that allows the co-fabrication of a diamond heat sink with the device gates so that the diamond heat spreader is in close proximity to the junction, and the ability to offer dual-side cooling without affecting the high frequency operation of the device.
The prior art includes the following.
1. K-C Chen et al, “Thermal Management and Novel Package Design of High Power Light Emitting Diodes”, National Cheng Kung University, Taiwan, Electronic Components and Technology Conference, 2008 describes a method for cooling high power light emitting diodes (LED) by doing electroless plating of Cu on the backside of the diode, which reduces junction temperature by up to 40° C. and thermal resistance by as much as 40%. However this does not address front-side cooling, near junction cooling and high frequency operation.
2. US Patent Application: US 2008/0298021 by A. A. Ali et al. discloses the use of CVD deposited thin film diamond for a heat spreader. The chip is mounted on thin film diamond using a TIM material (solder, thermal grease, phase change epoxy, or thin film metal: Ti/Pt/Au layer). The heat spreader is a thin film diamond, a diamond/copper hybrid, a diamond/aluminum hybrid, an aluminum or copper film. Also shown are different embodiments of their structure where heat pipes are embedded in the heat sink for an increased heat transfer coefficient. However, these approaches are not sufficient to cool 1 kW/cm2.
3. R. Feeler et al, “Next-Generation Microchannel Coolers”, Northrop Grumman, Proceedings of SPIE 2008, describes a micro-channel cooler for LED arrays using Low Temperature Co-Fired Ceramic (LTCC) material. They describe a heat sink made out of AlN, BeO or CVD diamond under the LED chip, which is connected the LTCC micro-channel. The CTE of LTCC is close to GaAs and InP so hard solder (AuSn) is used to mount the LED on the cooler. The LTTC addresses one major failure mechanism of copper micro-channels, which is their erosion when they are exposed to high water speeds. However, this approach has some disadvantages. First the distance between the backside of the chip and the cooling water is over 300 microns. It is critical to minimize this distance. In addition to that LTCC has low thermal conductivity (3.5 W/mK) compared to AIN (150 W/mK) and copper (400 W/mK). Thus, an additional thin film diamond or AIN heat sink is necessary under the LED chip.
4. US Patent Application US 2009/0294941A1 by J. Oh et al. describes a package-on-package system that includes mounting the chip on a base substrate, positioning an interposer over the chip and forming a heat spreader around the chip and the interposer. This approach focuses on multi-stacked chips and extracting heat from inside the stack by inserting the heat spreader between the packages as well as at the top of the module. The heat spreader surrounds the entire chip. However this approach has disadvantages. First it does not offer direct connection to the bottom of the chip, which is the primary area of heat dissipation coming from the active device junction. In contrast, heat is removed from the edges of the chip where solder is used to connect the heat sink to the chip, which is a very inefficient way to remove heat and definitely inadequate to handle wide band-gap components. Furthermore, the fact that the heat sink surrounds each chip makes integration of multiple chips difficult since significant component area around each chip is lost. Interconnection between different chips is impossible unless they are combined in a single heat sink and redesign of the heat sink will be necessary every time different chips are cooled.
5. US Patent Application US 2006/0027635 A1 by M. J. Schaenzer et al. describes a mounting method where the base of the heat sink is selectively plated with solder and connected to a heat spreader plated with Au. The heat sink is connected to the top of the chip. This approach is close to conventional cooling methods. The disadvantages of this is that it requires a high thermal resistance TIM material (solder) to transfer heat from the chip to the heat sink, it can be used for a single chip only and is not applicable to 3D multi-layer systems or multiple chips integrated in a single system, and it offers no solution for interconnecting multiple chips especially for high frequency applications.
6. More traditional cooling approaches that rely on mounting chips on various heat sinks are disclosed in the following: US 2009/0134421 A1 by G. H. Negley, US 2008/0099770 A1 by N. W. Mendendorp, US 2007/0247851 A1 by R. G. Villard, US 2006/0292747 A1 by B. P. Loh, and U.S. Pat. No. 7,579,626 B2 by A. W. Saxler.
7. US Patent Application US 2009/0108437 A1 by B. D. Raymond discloses a method of creating a heat sink by backside metallization of a wafer. This metallization is realized with composite electroplating of various metallic compounds with variable CTE. Some examples are Cu-Diamond, Cr-Diamond, or metallic compounds with Be, BeO and carbon nano-tubes. After the wafer is backside metalized, the individual chips are diced. This disclosure does not address front-side cooling and it blindly metalizes the entire wafer.
8. US Patent Application US 2006/0091509 A1 by S. Z. Zhao et al. disclosures a traditional cooling approach focusing on flip-chip interconnected packages including the formation of a cavity on the heat sink which allows for easier integration of the chip. The disadvantages of this approach are that it requires special machining of the heat sink and it still needs TIM materials for connecting the chip to the heat sink.
9. US 2008/0128897 A1 by T. W. Chao, describes a more conventional approach focusing on flip-chip mounted chips, which has disadvantages similar to Zhao above. US 2007/0075420 A1 by D. Lu et al, is similar to Raymond above, the main difference being that the devices are flip-chip mounted active face down to a board and then metalized from the back. Again metallic compounds are proposed for better CTE matching. However this does not offer the advantage of processing known-good-die because it requires flip-chip bonding on a board. This is a reliability concern since the solder bumps and the under-fill material used have higher thermal resistance. U.S. Pat. No. 7,492,041 B2, by K. Ravi et al. describes the combination of a Si wafer with a diamond wafer to form a heat sink on the backside of a silicon wafer. It does not address near junction heat removal and front-side cooling of devices.
10. U.S. Pat. No. 7,777,315 by J. Noqil describes a dual side cooling integrated power device module and methods of manufacture. However, the parts are integrated together using a molding material which is some form of resin, which is a low thermal conductivity material.
11. U.S. Pat. No. 6,989,592 by Chang et al., describes a dual side cooling approach using epoxy on the front side of the chip to transition heat from the front-side to a heat exchanger. This approach cannot be extended to high frequency power devices due to the epoxy that has to surround the interconnects and also is limited with respect to its heat flux removal rate by the thermal conductivity of the epoxy which is not high.
12. U.S. Pat. No. 7,538,423 by T. Ono et al., describes a way to fabricate a heat sink using insulating diamond at the backside of a wafer, which does not address the near junction of the device. Nor can it be used on the front-side of the device where the junction is exposed.
13. U.S. Pat. No. 7,749,863 by M. Micovic, describes a method for fabricating a thermal management substrate on a SOI silicon wafer. However, Micovic does not address two issue 1) the ability to make diamond heat spreaders on the front-side in close proximity to the junction and 2) the ability to remove heat from the front-side with the addition of front-side heat sinks.
What is needed is a better cooling approach for GaN devices. In particular what is needed are cooling approaches that allow the integration of high efficiency high performance spreaders on the front-side in close proximity to the junction and that have the ability to remove heat from the front-side with the addition of front-side heat sinks. The embodiments of the present disclosure answer these and other needs.